Draft

07_RISC-V

== Digital design meets computer architecture

RISC vs CISC and The RISC-V architecture

Existing processor types can be classified by their instruction type set: Reduced instruction set computer (RISC), Complex instruction set computer (CISC) and hybrid forms. While mini processors like ARM for embedded systems mostly utilise reduced instruction sets,todays workstation and Server Architectures (x86, x86_64) are hybrids of RISC and CISC. The idea of a reduced instruction set is to avoid big complex instructions and multiple different addressing modes (as those typically used in x86 architectures). Advantages of a RISC architecture are shorter pipelines which allows faster clocking. RISC architectures follow a simple scheme: 'Fetch → Decode → Fetch Operands → Execute → Write Back' Also instructions have a constant length, memory operations are divided from arithmetic operations, which is known as Load/Store-architecture. RISC-V is an open standard for the instruction set archtitecture (ISA). Most of this post is referenced from the popular book Computer Organization and Design (RISC-V) Edition by Hennessey and Patterson.

How does a CPU work? Overview

== How does a CPU work – Table of Contents

Introduction and Overview

Introduction and Overview

Each topic in this course is divided into two parts: one focusing on the mathematical side of digital logic— ideally independent of implementation details— and another more concrete part dealing with those very details. In the concrete part, we will mostly discuss implementations on the electrical level, although other solutions are possible, such as those based on fluid dynamics or optical gates.